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HD64F2149YV データシート(PDF) 471 Page - Renesas Technology Corp |
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HD64F2149YV データシート(HTML) 471 Page - Renesas Technology Corp |
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471 / 1075 page  Section 15 Serial Communication Interface (SCI, IrDA) Rev. 3.00 Jan 18, 2006 page 443 of 1044 REJ09B0280-0300 15.2.8 Bit Rate Register (BRR) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 0 1 R/W 2 1 R/W 1 1 R/W Bit Initial value Read/Write BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 15.3 shows sample BRR settings in asynchronous mode, and table 15.4 shows sample BRR settings in synchronous mode. |
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