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HD64F2149YV データシート(PDF) 536 Page - Renesas Technology Corp

部品番号 HD64F2149YV
部品情報  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV データシート(HTML) 536 Page - Renesas Technology Corp

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Section 16 I
2C Bus Interface
Rev. 3.00 Jan 18, 2006 page 508 of 1044
REJ09B0280-0300
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
Bit 5
Bit 4
MST
TRS
Operating Mode
0
0
Slave receive mode
(Initial value)
1
Slave transmit mode
1
0
Master receive mode
1
Master transmit mode
Bit 5
MST
Description
0
Slave mode
(Initial value)
[Clearing conditions]
1. When 0 is written by software
2. When bus arbitration is lost after transmission is started in I
2C bus format master
mode
1
Master mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing condition 2)
2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2)



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