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HD64F2149YV データシート(PDF) 602 Page - Renesas Technology Corp

部品番号 HD64F2149YV
部品情報  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV データシート(HTML) 602 Page - Renesas Technology Corp

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Section 17 Keyboard Buffer Controller
Rev. 3.00 Jan 18, 2006 page 574 of 1044
REJ09B0280-0300
Receive data processing
Clear KBF flag
(KCLK = H)
Processing 1
Receive operation ends
normally
[1] On the system side, drive the KCLK pin low,
setting the I/O inhibit state.
[1]
Transmit enabled state.
If there is transmit data,
the data is transmitted.
Figure 17.7 Sample Receive Abort Processing Flowchart (cont)
Keyboard side monitors clock during
receive operation (transmit operation
as seen from keyboard), and aborts
receive operation during this period.
KCLK
(pin state)
KD
(pin state)
KCLK
(input)
KCLK
(output)
KD
(input)
KD
(output)
Reception in progress
Receive abort request
Transmit operation
Start bit
Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover)
Timing



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