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HD64F2149YV データシート(PDF) 608 Page - Renesas Technology Corp

部品番号 HD64F2149YV
部品情報  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV データシート(HTML) 608 Page - Renesas Technology Corp

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Section 17 Keyboard Buffer Controller
Rev. 3.00 Jan 18, 2006 page 580 of 1044
REJ09B0280-0300
17.3.9
Usage Note
When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1.
Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit
operates and the KCLK falling edge is detected.
If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 17.14 shows the
timing of KBIOE setting and KCLK falling edge detection.
T1
T2
φ
KCLK (pin)
Internal KCLK
(KCLKI)
Falling edge
signal
KBIOE
KBFSEL
KBE
KBF
Figure 17.14 KBIOE Setting and KCLK Falling Edge Detection Timing



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