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HD64F2149YV データシート(PDF) 646 Page - Renesas Technology Corp |
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HD64F2149YV データシート(HTML) 646 Page - Renesas Technology Corp |
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646 / 1075 page  Section 18B Host Interface LPC Interface (LPC) Rev. 3.00 Jan 18, 2006 page 618 of 1044 REJ09B0280-0300 HICR2 Bit 4 ABRT Description 0 [Clearing conditions] (Initial value) • Writing 0 after reading ABRT = 1 • LPC hardware reset (LRESET pin falling edge detection) • LPC software reset (LRSTB = 1) • LPC hardware shutdown (SDWNE = 1 and LPCPD falling edge detection) • LPC software shutdown (SDWNB = 1) 1 [Setting condition] • LFRAME pin falling edge detection during LPC transfer cycle HICR2 Bit 3—IDR3 and TWR receive complete Interrupt Enable (IBFIE3) HICR2 Bit 2—IDR2 receive complete Interrupt Enable (IBFIE2) HICR2 Bit 1—IDR1 receive complete Interrupt Enable (IBFIE1) HICR2 Bit 0—Error Interrupt Enable (ERRIE) These bits enable or disable IBFI1, IBFI2, IBFI3, and ERRI interrupts to the slave processor. HICR2 Bit 3 HICR2 Bit 2 HICR2 Bit 1 HICR2 Bit 0 IBFIE3 IBFIE2 IBFIE1 ERRIE Description ———0 Error interrupt requests disabled (Initial value) ———1 Error interrupt requests enabled — — 0 — Input data register IDR1 receive completed interrupt request disabled (Initial value) — — 1 — Input data register IDR1 receive completed interrupt request enabled — 0 — — Input data register IDR2 receive completed interrupt request disabled (Initial value) — 1 — — Input data register IDR2 receive completed interrupt request enabled 0 ———Input data register IDR3 and TWR receive completed interrupt requests disabled (Initial value) 1 ———Input data register IDR3 and TWR receive completed interrupt requests enabled |
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