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HD64F2149YV データシート(PDF) 707 Page - Renesas Technology Corp |
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HD64F2149YV データシート(HTML) 707 Page - Renesas Technology Corp |
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707 / 1075 page ![]() Section 20 A/D Converter Rev. 3.00 Jan 18, 2006 page 679 of 1044 REJ09B0280-0300 If a filter capacitor is connected as shown in figure 20.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (R in), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC *1 AVref AN0 to AN7 AVSS Notes: Figures are reference values. 1. 2. Rin: Input impedance *1 Rin*2 100 Ω 0.1 µF 0.01 µF 10 µF Figure 20.7 Example of Analog Input Protection Circuit Table 20.5 Analog Pin Ratings Item Min Max Unit Analog input capacitance — 20 pF Permissible signal source impedance — 5* k Ω Note: * When V CC= 2.7 to 3.6 V and φ ≤ 10 MHz. |
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