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HD64F2149YV データシート(PDF) 178 Page - Renesas Technology Corp |
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HD64F2149YV データシート(HTML) 178 Page - Renesas Technology Corp |
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178 / 1075 page  Section 6 Bus Controller Rev. 3.00 Jan 18, 2006 page 150 of 1044 REJ09B0280-0300 6.4.3 Valid Strobes Table 6.5 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.5 Data Buses Used and Valid Strobes Area Access Size Read/ Write Address Valid Strobe Upper Data Bus (D15 to D8) Lower Data Bus (D7 to D0) Byte Read — RD Valid Port, etc. 8-bit access space Write — HWR Port, etc. Byte Read Even RD Valid Invalid 16-bit access space Odd Invalid Valid Write Even HWR Valid Undefined Odd LWR Undefined Valid Word Read — RD Valid Valid Write — HWR, LWR Valid Valid Notes: Undefined: Undefined data is output. Invalid: Input state; input value is ignored. Port, etc.: Pins are used as port or on-chip supporting module input/output pins, and not as data bus pins. |
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