HD64F2149YV datasheet(194/1075 Pages) RENESAS

部品番号	HD64F2149YV

部品情報	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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メーカー	RENESAS [Renesas Technology Corp]

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194 / 1075 page

Section 6 Bus Controller

Rev. 3.00 Jan 18, 2006 page 166 of 1044

REJ09B0280-0300

6.7.3

Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus

master that has acquired the bus and is currently operating, the bus is not necessarily transferred

immediately. There are specific times at which each bus master can relinquish the bus.

CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,

the bus arbiter transfers the bus to the DTC. The timing for transfer of the bus is as follows:

• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in

discrete operations, as in the case of a longword-size access, the bus is not transferred between

the operations.

See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not

transferred.

• If the CPU is in sleep mode, it transfers the bus immediately.

DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.

The DTC does not release the bus until it has completed a series of processing operations.

HD64F2149YV データシート(PDF) 194 Page - Renesas Technology Corp