HD64F2149YV datasheet(217/1075 Pages) RENESAS

データシートサーチシステム

HD64F2149YV データシート(PDF) 217 Page - Renesas Technology Corp

部品番号	HD64F2149YV

部品情報	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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メーカー	RENESAS [Renesas Technology Corp]

ホームページ	http://www.renesas.com

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217 / 1075 page

Section 7 Data Transfer Controller

Rev. 3.00 Jan 18, 2006 page 189 of 1044

REJ09B0280-0300

7.3.8

Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in

response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data

transfers, can be set independently.

Figure 7.9 shows memory mapping for chain transfer.

Source

Destination

DTC vector

address

start address

CHNE = 1

CHNE = 0

Figure 7.9 Memory Mapping in Chain Transfer

In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the

end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt

source flag for the activation source is not affected.

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