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データシートサーチシステム |
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H8SX/1663 データシート(PDF) 424 Page - Renesas Technology Corp |
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H8SX/1663 データシート(HTML) 424 Page - Renesas Technology Corp |
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424 / 1158 page  Section 7 DMA Controller (DMAC) Rev.1.00 Jun. 07, 2006 Page 372 of 1102 REJ09B0294-0100 Address bus DMA word write cycle DMA byte read cycle DMA byte read cycle DMA word read cycle DMA word write cycle DMA word write cycle DMA byte read cycle DMA byte read cycle DMA word read cycle DMA word write cycle B φ RD LLWR LHWR TEND Bus released Bus released Bus released Last transfer cycle 4m + 1 4m + 2 4m + 4 4n + 4 4n + 6 4n 4n +2 4m + 5 4m + 6 4m + 8 m and n are integers. Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment) DMA word read cycle DMA byte write cycle DMA word read cycle Address bus DMA byte write cycle DMA byte write cycle DMA word write cycle DMA word read cycle DMA byte write cycle DMA word read cycle DMA word write cycle B φ RD LLWR LHWR TEND Bus released Bus released Bus released Last transfer cycle 4m 4m + 2 4n + 5 4n + 2 4n + 4 4n + 6 4n + 8 4m + 4 4m + 6 4n + 1 m and n are integers. Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement) |
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