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H8SX/1663 データシート(PDF) 677 Page - Renesas Technology Corp |
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H8SX/1663 データシート(HTML) 677 Page - Renesas Technology Corp |
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677 / 1158 page  Section 12 8-Bit Timers (TMR) Rev.1.00 Jun. 07, 2006 Page 625 of 1102 REJ09B0294-0100 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.7 shows the TCNT count timing for internal clock input. Figure 12.8 shows the TCNT count timing for external clock input. Note that the external clock pulse width must be at least 1.5 states for increment at a single edge, and at least 2.5 states for increment at both edges. The counter will not increment correctly if the pulse width is less than these values. P φ Internal clock TCNT input clock TCNT N – 1 N N + 1 Figure 12.7 Count Timing for Internal Clock Input P φ External clock input pin TCNT input clock TCNT N – 1 N N + 1 Figure 12.8 Count Timing for External Clock Input |
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