H8SXSLASH1663 datasheet(1148/1158 Pages) RENESAS

1148 / 1158 page

Rev.1.00 Jun. 07, 2006 Page 1096 of 1102

REJ09B0294-0100

Control transfer....................................... 795

Counter operation ................................... 537

CPU priority control function over DTC

and DMAC ............................................. 125

CRC Operation Circuit ........................... 744

Crystal resonator..................................... 963

Cycle stealing mode................................ 354

D/A converter ......................................... 867

Data direction register ............................ 437

Data register............................................ 438

Data stage ............................................... 797

Data transfer controller (DTC) ............... 395

Direct convention ................................... 723

DMA controller (DMAC)....................... 317

Double-buffered structure....................... 698

Download pass/fail result parameter....... 893

DRAM interface ..................................... 228

DRAM Interface ..................................... 182

DTC vector address ................................ 407

DTC vector address offset ...................... 407

Dual address mode.................................. 343

Endian and data alignment...................... 189

Endian format ......................................... 180

Error protection ...................................... 925

Error signal ............................................. 723

Exception handling ................................... 77

Extended repeat area............................... 341

Extended repeat area function ................ 356

Extension of chip select (

CS) assertion

period...................................................... 202

External access bus................................. 168

External bus ............................................ 173

External bus clock (B

φ) .................. 169, 957

External bus interface ............................. 179

External clock ......................................... 964

External interrupts................................... 109

Flash erase block select parameter.......... 901

Flash memory ......................................... 875

Flash multipurpose address area

parameter ................................................ 899

Flash multipurpose data destination

parameter ................................................ 900

Flash pass and fail parameter .................. 894

Flash program/erase frequency

parameter ................................................ 898

Free-running count operation.................. 538

Frequency divider ........................... 957, 965

Full address mode ................................... 405

Full-scale error........................................ 861

General illegal instructions ....................... 89

Hardware protection................................ 924

Hardware standby mode ................. 972, 987

I/O ports .................................................. 429

I2C bus format......................................... 833

I2C bus interface2 (IIC2)......................... 817

ID code.................................................... 709

Idle cycle................................................. 291

Illegal instruction ...................................... 89

Input buffer control register .................... 439

Input capture function ............................. 541

Internal interrupts.................................... 110

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