M32CSLASH86 datasheet(90/505 Pages) RENESAS

部品番号	M32C/86

部品情報	RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

PDF	505 Pages

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メーカー	RENESAS [Renesas Technology Corp]

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Page 67

8. Bus

)

(

8.2.4.1 Bus Cycle with Recovery Cycle Added

The EWCRi06 bit in the EWCRi register (i=0 to 3) determines whether the recovery cycle is added or not.

In the recovery cycle, addresses and wrie data outputs are provided continuously (using the separate bus

only). Devices, which take longer address hold time and data hold time to write data, are connectable.

Figure 8.9 Recovery Cycle

A : Address

LA : Latch Address

RD : Read Data

WD : Write Data

• Recovery Cycle with Separate Bus (For 1

φ + 2φ)

BCLK

Address

CSi (1)

Data (Read)

Data (Write)

WR, WRL, WRH

Recovery Cycle

<--- Hold an Address

<--- Hold Data

• Recovery Cycle with Multiplexed Bus (For 2

φ + 3φ)

Recovery Cycle

<--- Hold Data

i=0 to 3

NOTES:

1. When the microcomputer continuously accesses the same CS area,

the CSi pin provides an "L" signal continuously.

BCLK

CSi (1)

Data (Read)

Data (Write)

WR (WRL)

ALE

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