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M32C/86 データシート(PDF) 307 Page - Renesas Technology Corp

部品番号 M32C/86
部品情報  RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  505 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C/86 データシート(HTML) 307 Page - Renesas Technology Corp

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22. Intelligent I/O
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22.3.2 Phase-Delayed Waveform Output Mode
Output signal level of the OUTC1j pin is inversed every time the base timer value matches the G1POj
register (j=0 to 7) setting. Table 22.10 lists specifications of phase-delayed waveform output mode.
Figure 22.17 lists an example of phase-delayed waveform output mode operation.
Table 22.10 Phase-Delayed Waveform Output Mode Specifications
Item
Specification
Output Waveform
• Free-running operation
(the RST2 and RST1 bits in the G1BCR1 register are set to "002")
Cycle
:
"H" and "L" widths
:
Setting value of the G1POj (j=0 to 7) register is 000016 to FFFF16
• The base timer is cleared to "000016" by matching the base timer with the
G1PO0 register (the RST1 bit is set to "1" and the RST2 bit is set to "0")
Cycle
:
"H" and "L" widths
:
n : setting value of the G1PO0 register, 000116 to FFFD16
Setting value of the G1POj (j=1 to 7) register is 000016 to FFFF16
If G1POj register
≥ n+2, the output level is not inversed
Waveform Output Start Condition(1) The IFEj bit (j=0 to 7) in the G1FE register is set to "1" (channel j function
enabled)
Waveform Output Stop Condition
The IFEj bit is set to "0" (channel j function disabled)
Interrupt Request
The PO1jR bit in the interrupt request register is set to "1" (interrupt
requested) when the base timer vslur matches the G1POj register setting.
(See Figure 11.14)
OUTC1j Pin
Pulse signal output pin
Selectable Function
• Default value set function: Set starting waveform output level
• Inversed output function
Waveform output level is inversed to output a waveform from the OUTC1j pin
NOTES:
1. Set the FSCj bit in the G1FS register to "0" (waveform generating function selected).
65536 x 2
fBT1
65536
fBT1
2(n+2)
fBT1
n+2
fBT1



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