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SH7052 データシート(PDF) 387 Page - Renesas Technology Corp

部品番号 SH7052
部品情報  SuperHTM RISC engine
PDF  919 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 データシート(HTML) 387 Page - Renesas Technology Corp

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IMF (ICF) Setting Timing in Compare-Match: The IMF bit and CMF bit are set to 1 in the
timer status register (TSR) by the compare-match signal generated when the general register (GR)
output compare register (OCR), or cycle register (CYLR) value matches the timer counter (TCNT)
value. The compare-match signal is generated in the last state of the match (when the matched
TCNT count value is updated).
The timing in this case is shown in figure 10.38.
CK
TCNT
GR(CYLR)
N
N
N + 1
TCNT input clock
Compare-match signal
Interrupt status flag
IMF (CMF)
Interrupt request signal
IMI (CMI)
Figure 10.38 IMF (CMF) Setting Timing in Compare-Match



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