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SH7052 データシート(PDF) 414 Page - Renesas Technology Corp |
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SH7052 データシート(HTML) 414 Page - Renesas Technology Corp |
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414 / 919 page  388 Contention between TCNT Write and Increment: If a write to a channel 0 to 11 free-running counter (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D, TCNT10A to TCNT10H, TCNT11), down-counter (DCNT8A to DCNT8P), or event counter 9 (ECNT9A to ECNT9F) is performed while that counter is counting up or down, the write to the counter has priority and the counter is not incremented or decremented. The timing in this case is shown in figure 10.65 In this example, the CPU writes H'5555 at the point at which TCNT is to be incremented from H'1001 to H'1002. Pø T1 TCNT address 5555 (CPU write value) Internal write signal TCNT input clock Address TCNT T2 1001 5556 Figure 10.65 Contention between TCNT Write and Increment |
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