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SH7052 データシート(PDF) 421 Page - Renesas Technology Corp |
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SH7052 データシート(HTML) 421 Page - Renesas Technology Corp |
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421 / 919 page  395 Contention between DCNT Write and Counter Clearing by Underflow: With the channel 8 down-counters (DCNT8A to DCNT8P), if the count is halted due to underflow occurring in the T2 state of a down-counter write cycle by the CPU, retention of the H'0000 value has priority and the write to DCNT by the CPU is not performed. Writing of 1 to the interrupt status flag (OSF) when the underflow occurs is performed in the same way as for normal underflow. The timing in this case is shown in figure 10.72. In this example, a write of H'5555 to DCNT is attempted at the same time as DCNT underflows. Pø T1 DCNT address Internal write signal DCNT input clock Underflow signal Address 5555 Write data DCNT Interrupt status flag (OSF) T2 0000 0000 0001 H'0000 retained when DCNT halts Figure 10.72 Contention between DCNT Write and Underflow |
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