SH7052 datasheet(469/919 Pages) RENESAS

469 / 919 page

443

Table 14.2

Registers (cont)

Channel

Name

Abbreviation R/W

Initial

Value

Address*

Access

Size

Serial mode register 3

SMR3

R/W

H'00

H'FFFFF018

8, 16

Bit rate register 3

BRR3

R/W

H'FF

H'FFFFF019

Serial control register 3

SCR3

R/W

H'00

H'FFFFF01A

Transmit data register 3

TDR3

R/W

H'FF

H'FFFFF01B

Serial status register 3

SSR3

R/(W)*

H'84

H'FFFFF01C

Receive data register 3

RDR3

H'00

H'FFFFF01D

Serial direction control

SDCR3

R/W

H'F2

H'FFFFF01E

Serial mode register 4

SMR4

R/W

H'00

H'FFFFF020

8, 16

Bit rate register 4

BRR4

R/W

H'FF

H'FFFFF021

Serial control register 4

SCR4

R/W

H'00

H'FFFFF022

Transmit data register 4

TDR4

R/W

H'FF

H'FFFFF023

Serial status register 4

SSR4

R/(W)*

H'84

H'FFFFF024

Receive data register 4

RDR4

H'00

H'FFFFF025

Serial direction control

SDCR4

R/W

H'F2

H'FFFFF026

Notes: 1. The only value that can be written is a 0 to clear the flags.

2. Do not access empty addresses.

3. In register access, four or five cycles are required for byte access, and eight or nine

cycles for word access.

14.2

14.2.1

Receive Shift Register (RSR)

The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into RSR

in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has

been received, it is automatically transferred to RDR.

The CPU cannot read or write to RSR directly.

Bit:

R/W:

—

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