SH7052 datasheet(159/919 Pages) RENESAS

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SH7052 データシート(PDF) 159 Page - Renesas Technology Corp

部品番号	SH7052

部品情報	SuperHTM RISC engine

PDF	919 Pages

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メーカー	RENESAS [Renesas Technology Corp]

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159 / 919 page

133

8.3.3

CS Assert Period Extension

Idle cycles can be inserted to prevent extension of the

RD, WRH, or WRL signal assert period

beyond the length of the

CSn signal assert period by setting the SW3 to SW0 bits of BCR2. This

allows for flexible interfaces with external circuitry. The timing is shown in figure 8.6. Th and Tf

cycles are added respectively before and after the ordinary cycle. Only

CSn is asserted in these

cycles;

RD, WRH, and WRL signals are not. Further, data is extended up to the T

f cycle, which is

effective for gate arrays and the like, which have slower write operations.

Read

Write

Address

CSn

Data

WRH, WRL

Data

Figure 8.6

CS Assert Period Extension Function

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