SH7708 datasheet(335/633 Pages) RENESAS

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11.4.2

Status Flag Clear Timing

The status flag can be cleared by writing a 0 from the CPU. Figure 11.9 shows the timing.

Peripheral address bus

UNF, ICPF

TCR address

TCR write cycle

Figure 11.9 Status Flag Clear Timing

11.4.3

Interrupt Sources and Priorities

The TMU produces underflow interrupts for each channel. When the interrupt request flag and

interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the exception

source register (INTEVT) for these interrupts and interrupt handling occurs according to the

codes.

The relative priorities of channels can be changed using the interrupt controller (see section 6,

Interrupt Controller) and section 4, Exception Handling. Table 11.3 lists TMU interrupt sources.

Table 11.3

TMU Interrupt Sources

Channel

Interrupt Source

Description

Priority

TUNI0

Underflow interrupt 0

High

TUNI1

Underflow interrupt 1

↑

TUNI2

Underflow interrupt 2

↓

TICPI2

Input capture interrupt 2

Low

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