SH7708 datasheet(371/633 Pages) RENESAS

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Bit 4—Framing Error (FER): Indicates that data reception aborted due to a framing error in

asynchronous mode.

Bit 4: FER

Description

Receiving is in progress or has ended normally.

(Initial value)

Clearing the RE bit to 0 in the serial control register does not affect the FER bit,

which retains its previous value.

FER is cleared to 0 when the chip is reset or enters standby mode or software

reads FER after it has been set to 1, then writes 0 in FER.

A receive framing error occurred.

When the stop bit length is two bits, only the first bit is checked. The second stop

bit is not checked. When a framing error occurs, the SCI transfers the receive

data into SCRDR but does not set RDRF. Serial receiving cannot continue while

FER is set to 1. In synchronous mode, serial transmitting is also disabled.

FER is set to 1 if the stop bit at the end of receive data is checked and found to

be 0.

Bit 3—Parity Error (PER): Indicates that data reception (with parity) aborted due to a parity error

in asynchronous mode.

Bit 3: PER

Description

Receiving is in progress or has ended normally.

(Initial value)

Clearing the RE bit to 0 in the serial control register does not affect the PER bit,

which retains its previous value.

PER is cleared to 0 when the chip is reset or enters standby mode or software

reads PER after it has been set to 1, then writes 0 in PER.

A receive parity error occurred.

When a parity error occurs, the SCI transfers the receive data into SCRDR but

does not set RDRF. Serial receiving cannot continue while PER is set to 1. In

synchronous mode, serial transmitting is also disabled.

PER is set to 1 if the number of 1s in receive data, including the parity bit, does

not match the even or odd parity setting of the parity mode bit (O/E) in the serial

mode register (SCSMR).

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