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SH7708 データシート(PDF) 437 Page - Renesas Technology Corp

部品番号 SH7708
部品情報  SuperH??RISC engine
PDF  633 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7708 データシート(HTML) 437 Page - Renesas Technology Corp

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419
0
185
371 0
185
371 0
Base clock
Receive
data (RxD)
Synchro-
nization
sampling
timing
Data
sampling
timing
186 clock cycles
372 clock cycles
Start
bit
D0
D1
Figure 14.8 Receive Data Sampling Timing in Smart Card Mode
The receive margin is found from the following equation:
For smart card mode:
M = (0.5 –
)
1
2N
D – 0.5
N
– (L – 0.5)F –
(1 + F)
× 100%
Where:
M = Receive margin (%)
N = Ratio of bit rate to clock (N = 372)
D = Clock duty (D = 0 to 1.0)
L = Frame length (L = 10)
F = Absolute value of clock frequency deviation
Using this equation, the receive margin when F = 0 and D = 0.5 is as follows:
M = (0.5 – 1/2
× 372) × 100% = 49.866%



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