CS47048 Data Sheet

Audio SOC Processor Family

10

Copyright 2008 Cirrus Logic

DS787A7

4.3.3 Digital Audio Input Port (DAI)

The input capabilities for each version of the CS47048 are summarized in Table 2 on page 7.

Up to five DAI ports are available. Two of the DAI ports can be programmed to implement other

functions. The S/PDIF Rx function, if used, takes over the DAI_DATA3 pin. If the SPI mode is used,

the DAI_DATA4 pin becomes the SCP_CS input.

The DAI port supports PCM format with word lengths up to 32 bits and sample rates as high as

192 kHz.

The DAI also supports a time division multiplexed (TDM) one-line data mode that packs PCM audio

on a single data line. The total number possible depends on the ratio of SCLK to LRCLK. The

CS47048 hardware supports up to 40 channels in one line mode @ 48 kHz. There is also a

practical limitation set by the amount of processing required per channel.

The DAI port has two independent slave-only clock domains. The PCM inputs can be on one clock

domain, and the S/PDIF Rx on another. The output of the S/PDIF Rx can then be converted

through one of the internal SRC blocks to synchronize with the PCM input.

The sample rate of the input clock domains can be determined automatically by the DSP, off-

loading the task of monitoring the S/PDIF Rx from the host. A time-stamping feature provides the

ability to also sample-rate convert the input data via software.

4.3.4 S/PDIF RX Input Port (DAI)

One of the PCM pins of the DAI can also be used as a DC-coupled, TTL-level S/PDIF Rx input

capable of receiving and demodulating bi-phase encoded S/PDIF signals with Fs

4.3.5 Digital Audio Output Port (DAO)

The output capabilities of the CS47048 are summarized in Table 2 on page 7.

DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high

as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or

as a clock slave if an external MCLK or SCLK/LRCLK source is available.

The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple

channels of PCM audio on a single data line. The total number possible depends on the ratio of

SCLK to LRCLK and the version of chip. For example, the CS47048 hardware supports up to 32

channels in one line mode @ 48 kHz. There is also a practical limitation set by the amount of

processing required per channel.

4.3.6 S/PDIF TX Output Port (DAO)

Two of the serial audio pins can be re-configured as S/PDIF TX pins that drive a bi-phase encoded

S/PDIF signal (data with embedded clock on a single line). The S/PDIF engine can be driven by a

clock domain independent of the PCM output port by utilizing one of the internal SRCs.

4.3.7 Sample Rate Converters (SRC)

The CS47048 has 3 internal SRC modules. Two of the SRC modules are capable of converting 8

Channels, and one SRC has 4-Channel capability.

The ADCs are directly associated with a 4-Channel SRC which is used to transfer data from the

fixed 96/192 kHz Fs domain into an Fs appropriate for mixing with other audio in the system. When

the Analog Inputs are not being used, this SRC can be used to convert digital data within the DSP

from the input Fs (Fsi) to the output Fs (Fso).

The DACs are directly associated with an 8-Channel SRC which is used to transfer data from the

Fs being processed by the DSP to a fixed 96 kHz Fs domain for conversion to analog. When the

Analog Outputs are not being used, this SRC can be used to convert digital data within the DSP

from Fsi to Fso.