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CS47048 データシート(PDF) 28 Page - Cirrus Logic

部品番号 CS47048
部品情報  Audio SOC Processor Family
PDF  34 Pages
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47048 データシート(HTML) 28 Page - Cirrus Logic

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CS47048 Data Sheet
Audio SOC Processor Family
28
Copyright 2008 Cirrus Logic
DS787A7
5.17.2 Analog Output Characteristics (Automotive)
(Test Conditions (unless otherwise specified): TA = -40 to +85°C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz
sine wave driven through a filter shown in Figure 13 on page 28 or Figure 14 on page 29; DSP running test applica-
tion; Measurement Bandwidth is 20 Hz to 20 kHz.)
Notes:
1. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical
leakage through the electrolytic DC-blocking capacitors.
2. Guaranteed by design. RL and CL reflect the recommended minimum resistance and maximum capacitance
required for the internal op-amp's stability and signal integrity. In this circuit topology, CL represents any capacitive
loading that appears before the 560
Ω series resistor (typically parasitic), and will effectively move the dominant pole
of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the
internal op-amp to become unstable.
Figure 13. DAC Single-Ended Output Test Circuit
Parameter
Differential
Min
Typ
Max
Single-Ended
Min
Typ
Max
Unit
Fs = 96 kHz
Dynamic Range
A-weighted
unweighted
100
97
108
105
-
-
97
94
105
102
-
-
dB
dB
Total Harmonic Distortion + Noise
0 dB
-20 dB
-60 dB
-
-
-
-98
-88
-48
-90
-
-
-
-
-
-95
-85
-45
-87
-
-
dB
dB
dB
Interchannel Isolation
(1 kHz)
-
95
-
-
95
-
dB
Analog Output
Full-Scale Output
TBD
1.35•VA
TBD
TBD
0.68•VA
TBD
VPP
Interchannel Gain Mismatch
-
0.1
-
-
0.1
-
dB
Gain Drift
-
±120
-
-
±120
-
ppm/°C
Output Impedance
-
100
-
-
100
-
Ω
DC Current draw from an AOUT pin1
--
10
-
-
10
μA
AC-Load Resistance (RL)
2
3-
-
3
-
-
k
Ω
Load Capacitance (CL)
2
-
-
100
-
-
100
pF
AOUT_x+
3.3 µF
CL
RL
AOUT
2200pF
560
10k



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