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TIR2000 データシート(PDF) 39 Page - Texas Instruments

部品番号 TIR2000
部品情報  High-Speed Serial Infrared Controller With 64-Byte FIFO
PDF  63 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

TIR2000 データシート(HTML) 39 Page - Texas Instruments

Back Button TIR2000 Datasheet HTML 35Page - Texas Instruments TIR2000 Datasheet HTML 36Page - Texas Instruments TIR2000 Datasheet HTML 37Page - Texas Instruments TIR2000 Datasheet HTML 38Page - Texas Instruments TIR2000 Datasheet HTML 39Page - Texas Instruments TIR2000 Datasheet HTML 40Page - Texas Instruments TIR2000 Datasheet HTML 41Page - Texas Instruments TIR2000 Datasheet HTML 42Page - Texas Instruments TIR2000 Datasheet HTML 43Page - Texas Instruments Next Button
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4–3
MIR/FIR (DMA) Mode
Bit No
7
6
5
4
3
2
1
0
Definition
Not
used
DMA
TC
asserted
TX
underrun
Status
FIFO
threshold
Not
used
Status FIFO
time-out
Not used
Not used
Default
0
0
0
0
0
0
0
0
Bit definition:
BIT NO.
DESCRIPTIONS
0
Not used
1
Not used
2
Status FIFO time-out interrupt pending. Bit 2 is cleared to 0 by reading the Status FIFO.
3
Not used
4
Status FIFO threshold interrupt pending. Bit 4 is cleared to 0 by reading the Status FIFO.
5
Transmit underrun pending. Bit 5 is set to a 1 when an underrun occurs in the data transmit FIFO. Bit 5 is
cleared to 0 by servicing the underrun.
6
DMA terminal count occurred interrupt pending. In the DMA mode, bit 6 is set to 1 when the terminal count
(TC) is asserted. Bit 6 is cleared to 0 by reading the Status FIFO.
7
Not used
TV Mode
IIR_TV
Bit No
7
6
5
4
3
2
1
0
Definition
0
0
TX
underrun
error
0
RX FIFO
overrun error
0
TX FIFO
below
threshold
RX FIFO
over
threshold
Default
0
0
0
0
0
0
1
0
Bit definition:
BIT NO.
DESCRIPTIONS
0
Receiver interrupt pending. Bit 0 is set to a 1 when the receiver FIFO level is equal to or above its threshold
level.
1
Transmitter interrupt pending. Bit 1 is set to a one when the transmitter FIFO level is below its threshold level.
2
always 0
3
Receiver FIFO overrun interrupt. Bit 3 is set to a one when an overrun occurs in the data RX FIFO.
4
always 0
5
Transmit underrun interrupt pending. Bit 5 is set to a one when an underrun occurs in the data transmit FIFO.
6
always 0
7
always 0



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