TIR2000 datasheet(10/63 Pages) TI

10 / 63 page

1–4

1.5

Terminal Functions

TERMINALS

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

A0 – A3

36–39

Address bus. The CPU uses A0 -A3 and the CS signal to select the internal register

of the TIR2000. A0 -A3 are decoded to select a particular register.

Chip select. The CPU uses CS to select the TIR2000 for read/write transactions.

CTS

Clear to send. CTS is a modem-status signal. Its condition can be checked by reading

bit 4 (CTS) of the modem-status register (MSR). Bit 0 (

∆CTS) of the MSR indicates

that CTS has changed states since the last read from the MSR. When modem-status

interrupt is enabled, CTS changes states, and the auto-CTS mode is not enabled, an

interrupt is generated. CTS is also used in the auto-CTS mode to control the

transmitter.

D0–D7

1–4,

6–9

I/O

Data bus. These bidirectional data lines are connected to the CPU for data transfer

between the TIR2000 and the CPU. D0 is the LSB and D7 is the MSB.

DACK0,

DACK1,

DACK3

27–29

DMA acknowledge. DACK0, DACK1, and DACK3 are DMA active low signals that

are the corresponding acknowledge signals, for the DMA request signals which are

DRQ0, DRQ1 and DRQ3.

DCD

Data carrier detect. DCD is a modem-status signal. Its condition can be checked by

reading bit 7 (DCD) of the MSR. Bit 3 (

∆DCD) of the MSR indicates that DCD has

changed states since the last read from the MSR. When the modem-status interrupt

is enabled and DCD changes state, an interrupt is generated.

DRQ0, DRQ1,

DRQ3

23–25

DMA requests. DRQ0, DRQ1 and DRQ3 are used for DMA requests that are active

high and are used to signal the DMA controller that data transfer between the

TIR2000 and memory is required. When the DMA is enabled, one of the three

channels configurable through the DMA channel select register (DCSR) can be

selected.

DSR

Data set ready. DSR is a modem-status signal. Its condition can be checked by

reading bit 5 (DSR) of the MSR. Bit 1 (

∆DSR) of the MSR indicates the DSR has

changed states since the last read from the MSR. When the modem-status interrupt

is enabled and the DSR changes states, an interrupt is generated.

DTR

Data terminal ready. When low, DTR informs a modem or data set that the UART is

ready to establish communication. DTR is placed in the active state by setting the

DTR bit of the modem-control register to one. DTR is placed in the inactive condition

as a result of a master reset, during loop mode operation, or clearing of the DTR bit.

GND

5, 10,

26, 34,

Ground (0 V). GND terminals must be tied to ground for proper operation.

GPIO0–GPIO3,

GPIO4–GPIO7

40–43,

45–48

I/O

General purpose I/O terminals. GPIO0–GPIO7 terminals are programmable

general-purpose input/output terminals.

IRQ3–IRQ7,

IRQ9–IRQ12,

IRQ14, IRQ15

11–16,

18–22

Interrupt signals. These active-high interrupts are activated based on the IRQ

configuration register.

IRRVH

Infrared receive. IRRVH is an input connected to the IR transceiver module that

receives data in the high-speed modes (1.15 Mbps and 4 Mbps mode).

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