LTM4619EVPBF datasheet(17/24 Pages) LINER

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LTM4619

4619f

APPLICATIONS INFORMATION

Figure 17. Recommended PCB Layout

TOP VIEW

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911

PGND

VIN

PGND

VOUT2

VOUT1

COUT1

COUT2

CIN2

CIN1

Layout Checklist/Example

The high integration of LTM4619 makes the PCB board

layout very simple and easy. However, to optimize its electri-

cal and thermal performance, some layout considerations

are still necessary.

• Use large PCB copper areas for high current path, includ-

ing VIN, PGND, VOUT1 and VOUT2. It helps to minimize

the PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-

tors next to the VIN, PGND and VOUT pins to minimize

high frequency noise.

• Place a dedicated power ground layer underneath the

unit.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnections

between top layer and other power layers.

• Do not put vias directly on the pad.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to PGND underneath the unit.

• Decouple the input and output grounds to lower the

output ripple noise. Refer to Figure 17.

Figure 17 gives a good example of the recommended

layout.

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