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SPT5420SIM データシート(PDF) 4 Page - Cadeka Microcircuits LLC.

部品番号 SPT5420SIM
部品情報  13-BIT, OCTAL D/A CONVERTER
PDF  8 Pages
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メーカー  CADEKA [Cadeka Microcircuits LLC.]
ホームページ  http://www.cadeka.com
Logo CADEKA - Cadeka Microcircuits LLC.

SPT5420SIM データシート(HTML) 4 Page - Cadeka Microcircuits LLC.

  SPT5420SIM Datasheet HTML 1Page - Cadeka Microcircuits LLC. SPT5420SIM Datasheet HTML 2Page - Cadeka Microcircuits LLC. SPT5420SIM Datasheet HTML 3Page - Cadeka Microcircuits LLC. SPT5420SIM Datasheet HTML 4Page - Cadeka Microcircuits LLC. SPT5420SIM Datasheet HTML 5Page - Cadeka Microcircuits LLC. SPT5420SIM Datasheet HTML 6Page - Cadeka Microcircuits LLC. SPT5420SIM Datasheet HTML 7Page - Cadeka Microcircuits LLC. SPT5420SIM Datasheet HTML 8Page - Cadeka Microcircuits LLC.  
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4
6/26/01
SPT5420
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Address Valid to WR Setup
t1
20
ns
Address Valid to WR Hold
t2
0ns
CS
Pulse Width Low
t3
50
ns
WR
Pulse Width Low
t4
50
ns
CS
to WR Setup
t5
0ns
WR
to CS Hold
t6
0ns
Data Setup
t7
25
ns
Data Hold
t8
0ns
Settling Time1
t9
15
us
LDAC
Pulse Width Low
t10
50
ns
CLR
Pulse Activation
t11
300
ns
NOTES:
All digital input rise and fall times are measured from 10% to 90% of +5 V.
tr = tf = 5 ns.
1. RL = 10 kΩ
CL ≤ 220 pF
TIMING CHARACTERISTICS
t5
t3
t6
t4
t1
t2
t7
t8
t10
CS
WR
A0–A2
D0–D12
LDAC
t9
VOUT
t5
t3
t6
t4
t1
t2
t7
t8
CS
WR
A0–A2
D0–D12
t9
VOUT
t11
t9
CLR
VOUT
Figure 1a – Timing Diagram: Latched Mode
(LDAC Strobed)
Figure 1b – Timing Diagram: Transparent Mode
(LDAC Held Low)



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