DM9102DEP datasheet(52/70 Pages) DAVICOM

部品番号	DM9102DEP

部品情報	Single Chip Fast Ethernet NIC Controller

PDF	70 Pages

Scroll/Zoom	100%

メーカー	DAVICOM [Davicom Semiconductor, Inc.]

ホームページ	http://www.davicom.com.tw

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52 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

The operational sequence from D0 to D3 should be:

Stop TX/RX process

wait for entering stop state

set

test mode, CR6<28:25> = 0011

programming FIFO

contents

exit test mode

enter D3 (hot) state

The sample frame data comparison is completed when the

received frame data has exceeded the programmed frame

length or when the whole packet has been fully received.

The operation procedure is shown below.

CR13: Sample Frame Access Register

Name

General definition

Bit8:3

Type

TxFIFO

Transmit FIFO access port

32h

R/W

RxFIFO

Receive FIFO access port

35h

DiagReset

General reset for diagnostic pointer port

38h

In DiagReset port there are 7 bits:

Bit 0: Clear TX FIFO write_ address to 0

Bit 1: Clear TX FIFO read_ address to 0

Bit 2: Clear RX FIFO write_ address to 0

Bit 3: Clear RX FIFO read_ address to 0

Bit 4: Reserved

Bit 5: Set TX FIFO write_ address to 080H

Bit 6: Set RX FIFO write_ address to 080H

DM9102DEP データシート(PDF) 52 Page - Davicom Semiconductor, Inc.

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