X24026

7

Current Address Read

Internally the X24026 contains an address counter that

maintains the address of the last word accessed, incre-

mented by one. Therefore, if the last access (either a

read or write) was to address n, the next read operation

would access data from address n + 1. Upon receipt of

the slave address with the R/W bit set to one, the X24026

issues an acknowledge and transmits the eight bit word

during the next eight clock cycles. The master terminates

this transmission by issuing a stop condition, omitting the

ninth clock cycle acknowledge. Refer to Figure 7 for the

sequence of address, acknowledge and data transfer.

Random Read

Random read operations allow the master to access any

memory location in a random manner. Prior to issuing

the slave address with the R/W bit set to one, the master

must first perform a “dummy” write operation. The master

issues the start condition, and the slave address followed

by the word address it is to read. After the word address

acknowledge, the master immediately reissues the start

condition and the slave address with the R/W bit set to

one. This will be followed by an acknowledge from the

X24026 and then by the eight bit word. The master termi-

nates this transmission by issuing a stop condition, omit-

ting the ninth clock cycle acknowledge. Refer to Figure 8

for

the

address,

acknowledge

and

data

transfer

sequence.

Figure 7. Current Address Read

Figure 8. Random Read

7020 FRM 10

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BUS ACTIVITY:

MASTER

SDA LINE

X24026

BUS ACTIVITY:

SLAVE

ADDRESS

DATA

7020 FRM 11

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WORD

ADDRESS n

SLAVE

ADDRESS

DATA n

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T

A

R

T

S

BUS ACTIVITY:

MASTER

SDA LINE

X24026

BUS ACTIVITY:

SLAVE

ADDRESS