P89LPC9331FDH datasheet(62/93 Pages) NXP

62 / 93 page

P89LPC9331_9341_9351_9361_3

Product data sheet

Rev. 03 — 2 June 2009

62 of 93

NXP Semiconductors

P89LPC9331/9341/9351/9361

8-bit microcontroller with accelerated two-clock 80C51 core

8.6 ADC operating modes

8.6.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be

performed and the result placed in the result register pair which corresponds to the

selected input channel. An interrupt, if enabled, will be generated after the conversion

completes.

In P89LPC9351/9361, in ﬁxed channel mode, the PGA channel selection is dependent on

the ADC channel selection. If PGA is enabled, all the selected channels for A/D

conversion will be ampliﬁed and the gain amplify level is the same.

8.6.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the

conversions will be sequentially placed in the four result register. The user may select

whether an interrupt can be generated after every four conversions. Additional conversion

results will again cycle through the four result register, overwriting the previous results.

Continuous conversions continue until terminated by the user.

In P89LPC9351/9361, in ﬁxed channel mode, the PGA channel selection is independent

and can be different to A/D conversion channel selection. If different, the gain of the

selected ADC channel is 1.

8.6.3 Auto scan, single conversion mode

Any combination of the four input channels can be selected for conversion. A single

conversion of each selected input will be performed and the result placed in the result

generated after all selected channels have been converted. If only a single channel is

selected this is equivalent to single channel, single conversion mode.

In P89LPC9351/9361, in auto scan mode, the PGA channel selection is dependent on the

ADC channel selection. If PGA is enabled, all the selected channel for A/D conversion will

be ampliﬁed and the gain amplify level is the same.

8.6.4 Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion. A conversion

of each selected input will be performed and the result placed in the result register which

corresponds to the selected input channel. An interrupt, if enabled, will be generated after

all selected channels have been converted. The process will repeat starting with the ﬁrst

selected channel. Additional conversion results will again cycle through the eight result

terminated by the user.

In P89LPC9351/9361, in auto scan mode, the PGA channel selection is dependent on the

ADC channel selection. If PGA is enabled, all the selected channel for A/D conversion will

be ampliﬁed and the gain amplify level is the same.

8.6.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs

on two user-selectable inputs. The result of the conversion of the ﬁrst channel is placed in

the result register, ADxDAT0. The result of the conversion of the second channel is placed

P89LPC9331FDH データシート(PDF) 62 Page - NXP Semiconductors

P89LPC9331FDH データシート(HTML) 62 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

データシートダウンロード