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ADT7462ACPZ-R7 データシート(PDF) 72 Page - ON Semiconductor

部品番号 ADT7462ACPZ-R7
部品情報  Flexible Temperature, Voltage Monitor, and System Fan Controller
PDF  81 Pages
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

ADT7462ACPZ-R7 データシート(HTML) 72 Page - ON Semiconductor

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72
Table 68. Register 0x35 — Digital Mask Register (Note 1)
Bit
Name
R/W
Description
[2:0]
Reserved
R
Reserved for future use.
3
FAN2MAX
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
4
SCSI1
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
5
SCSI2
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
6
VID Comparison
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
7
Chassis Intrusion
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
1. POR = 0x38, Lock = N, SW Reset = Y.
Table 69. Register 0x36 — GPIO Mask Register (Note 1)
Bit
Name
R/W
Description
0
GPIO1
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
1
GPIO2
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
2
GPIO3
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
3
GPIO4
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
4
GPIO5
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
5
GPIO6
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
6
GPIO7
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
7
GPIO8
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 70. Register 0x37 — EDO 1 Mask Register (Note 1)
Bit
Name
R/W
Description
0
GPIO1
R/W
A 1 masks GPIO1 from causing an EDO1 assertion.
1
GPIO2
R/W
A 1 masks GPIO2 from causing an EDO1 assertion.
2
GPIO3
R/W
A 1 masks GPIO3 from causing an EDO1 assertion.
3
GPIO4
R/W
A 1 masks GPIO4 from causing an EDO1 assertion.
4
Reserved
R/W
Unused.
5
Fan
R/W
A 1 masks a fan−fail condition from causing an EDO1 assertion.
6
Temp
R/W
A 1 masks a THERM condition from causing an EDO1 assertion.
7
Volt
R/W
A 1 masks a voltage exceed limit condition from causing an EDO1 assertion.
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 71. Register 0x38 — EDO 2 Mask Register (Note 1)
Bit
Name
R/W
Description
0
GPIO1
R/W
A 1 masks GPIO1 from causing an EDO2 assertion.
1
GPIO2
R/W
A 1 masks GPIO2 from causing an EDO2 assertion.
2
GPIO3
R/W
A 1 masks GPIO3 from causing an EDO2 assertion.
3
GPIO4
R/W
A 1 masks GPIO4 from causing an EDO2 assertion.
4
Reserved
R/W
Unused.
5
Fan
R/W
A 1 masks a fan−fail condition from causing an EDO2 assertion.
6
Temp
R/W
A 1 masks a THERM condition from causing an EDO2 assertion.
7
Volt
R/W
A 1 masks a voltage exceed limit condition from causing an EDO2 assertion.
1. POR = 0x00, Lock = N, SW Reset = Y.



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