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MPC8535E データシート(PDF) 22 Page - Freescale Semiconductor, Inc |
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MPC8535E データシート(HTML) 22 Page - Freescale Semiconductor, Inc |
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22 / 126 page  MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3 Overall DC Electrical Characteristics Freescale Semiconductor 22 2.1.2 Recommended Operating Conditions Table 3 provides the recommended operating conditions for this device. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 2. Absolute Maximum Ratings1 Characteristic Symbol Max Value Unit Notes Core supply voltage VDD_CORE –0.3 to 1.21 V — Platform supply voltage VDD_PLAT –0.3 to 1.1 V — PLL core supply voltage AVDD_CORE –0.3 to 1.21 V — PLL other supply voltage AVDD –0.3 to 1.1 V — Core power supply for SerDes transceivers SVDD, S2VDD –0.3 to 1.1 V — Pad power supply for SerDes transceivers and PCI Express XVDD, X2VDD –0.3 to 1.1 V — DDR SDRAM Controller I/O supply voltage DDR2 SDRAM Interface GVDD –0.3 to 1.98 V — DDR3 SDRAM Interface –0.3 to 1.65 Three-speed Ethernet I/O, MII management voltage LVDD (eTSEC1) –0.3 to 3.63 –0.3 to 2.75 V2 TVDD (eTSEC3) –0.3 to 3.63 –0.3 to 2.75 V2 PCI, DUART, system control and power management, I2C, USB, eSDHC, eSPI and JTAG I/O voltage OVDD –0.3 to 3.63 V — Local bus I/O voltage BVDD –0.3 to 3.63 –0.3 to 2.75 –0.3 to 1.98 V— Input voltage DDR2/DDR3 DRAM signals MVIN –0.3 to (GVDD + 0.3) V 3 DDR2/DDR3 DRAM reference MVREF –0.3 to (GVDD + 0.3) V — Three-speed Ethernet signals LVIN TVIN –0.3 to (LVDD + 0.3) –0.3 to (TVDD + 0.3) V3 Local bus signals BVIN –0.3 to (BVDD + 0.3) — — PCI, DUART, SYSCLK, system control and power management, I2C, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 3 Storage temperature range TSTG –55 to 150 0C— Notes: 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. The 3.63-V maximum is only supported when the port is configured in GMII, MII, RMII or TBI modes; otherwise the 2.75V maximum applies. See Section 2.9.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on the recommended operating conditions per protocol. 3. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. |
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