MPC8535E datasheet(76/126 Pages) FREESCALE

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MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3

Programmable Interrupt Controller (PIC)

Freescale Semiconductor

Figure 43 provides the eSDHC clock input timing diagram.

Figure 43. eSDHC Clock Input Timing Diagram

Figure 44 provides the data and command input/output timing diagram.

Figure 44. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock

2.14

Programmable Interrupt Controller (PIC)

In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain

the assertion for at least 3 system clocks (SYSCLK periods).

2.15

JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8535E.

2.15.1

JTAG DC Electrical Characteristics

Table 57 provides the DC electrical characteristics for the JTAG interface.

Table 57. JTAG DC Electrical Characteristics

Parameter

Symbol 1

Min

Max

Unit

High-level input voltage

VIH

2OVDD + 0.3

Low-level input voltage

VIL

-0.3

0.8

eSDHC

tSHSCKR

External Clock

tSHSCK

tSHSCKF

VM = Midpoint Voltage (OVDD/2)

operational mode

tSHSCKL

tSHSCKH

VM = Midpoint Voltage (OVDD/2)

SD_CK

External Clock

SD_DAT/CMD

Inputs

SD_DAT/CMD

Outputs

tSHSIVKH

tSHSIXKH

tSHSKHOV

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