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CY8C52 データシート(PDF) 39 Page - Cypress Semiconductor |
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CY8C52 データシート(HTML) 39 Page - Cypress Semiconductor |
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39 / 94 page  PRELIMINARY PSoC® 5: CY8C52 Family Datasheet Document Number: 001-66236 Rev. ** Page 39 of 94 Figure 7-13. Digital System Interconnect Interrupt and DMA routing is very flexible in the CY8C52 programmable architecture. In addition to the numerous fixed function peripherals that can generate interrupt requests, any data signal in the UDB array routing can also be used to generate a request. A single peripheral may generate multiple independent interrupt requests simplifying system and firmware design. Figure 7-14 shows the structure of the IDMUX (Interrupt/DMA Multiplexer). Figure 7-14. Interrupt and DMA Processing in the IDMUX 7.4.1 I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 for data and four for drive strength control. When an I/O pin is connected to the routing, there are two primary connections available, an input and an output. In conjunction with drive strength control, this can implement a bidirectional I/O pin. A data output signal has the option to be single synchronized (pipelined) and a data input signal has the option to be double synchronized. The synchronization clock is the system clock (see Figure 6-1). Normally all inputs from pins are synchronized as this is required if the CPU interacts with the signal or any signal derived from it. Asynchronous inputs have rare uses. An example of this is a feed through of combinational PLD logic from input pins to output pins. Figure 7-15. I/O Pin Synchronization Routing Figure 7-16. I/O Pin Output Connectivity There are four more DSI connections to a given I/O port to implement dynamic output enable control of pins. This connectivity gives a range of options, from fully ganged 8-bits controlled by one signal, to up to four individually controlled pins. The output enable signal is useful for creating tristate bidirectional pins and buses. Figure 7-17. I/O Pin Output Enable Connectivity UDB ARRAY Digital System Routing I/F Digital System Routing I/F CAN Interrupt Controller I2C IO Port Pins DMA Controller IO Port Pins Del-Sig Comparators DACs SC/CT Blocks Global Clocks EMIF Global Clocks Timer Counters DMA termout (IRQs) DMA Controller Interrupt Controller Fixed Function IRQs Edge Detect Edge Detect IRQs UDB Array Fixed Function DRQs DRQs Interrupt and DMA Processing in IDMUX 0 1 2 3 0 1 2 DO DI Port i PIN 0 DO PIN1 DO PIN2 DO PIN3 DO PIN4 DO PIN5 DO PIN6 DO PIN7 DO 8 IO Data Output Connections from the UDB Array Digital System Interface Port i PIN 0 OE PIN1 OE PIN2 OE PIN3 OE PIN4 OE PIN5 OE PIN6 OE PIN7 OE 4 IO Control Signal Connections from UDB Array Digital System Interface [+] Feedback [+] Feedback [+] Feedback |
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