CY8C52 datasheet(21/94 Pages) CYPRESS

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PRELIMINARY

PSoC® 5: CY8C52 Family Datasheet

Document Number: 001-66236 Rev. **

Page 21 of 94

Four 16-bit clock dividers generate clocks for the analog system

components that require clocking, such as the ADC. The

analog clock dividers include skew control to ensure that critical

analog events do not occur simultaneously with digital

switching events. This is done to reduce analog system noise.

Each clock divider consists of an 8-input multiplexer, a 16-bit

clock divider (divide by 2 and higher) that generates ~50% duty

cycle clocks, system clock resynchronization logic, and deglitch

logic. The outputs from each digital clock tree can be routed into

the digital system interconnect and then brought back into the

clock system as an input, allowing clock chaining of up to 32 bits.

6.1.4 USB Clock Domain

The USB clock domain is unique in that it operates largely

asynchronously from the main clock network. The USB logic

contains a synchronous bus interface to the chip, while running

on an asynchronous clock to process USB data. The USB logic

requires a 48 MHz frequency. This frequency is generated from

the doubled value of 24 MHz from internal oscillator, DSI signal,

or crystal oscillator.

6.2 Power System

The power system consists of separate analog, digital, and I/O

supply pins, labeled VDDA, VDDD, and Vddiox, respectively. It

also includes two internal 1.8 V regulators that provide the digital

(VCCD) and analog (VCCA) supplies for the internal core logic.

The output pins of the regulators (VCCD and VCCA) and the VDDIO

pins must have capacitors connected as shown in Figure 6-4.

The two VCCD pins must be shorted together, with as short a

trace as possible, and connected to a 1 µF ±10% X5R capacitor.

The power system also contains a sleep regulator and a

hibernate regulator.

Figure 6-4. PSoC Power System

Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as

shown in Figure 2-4.

Vssd

Vddio0

Vssa

Vcca

Vdda

Digital

Regulators

Analog

Regulator

Analog

Domain

Digital

Domain

I2C

Regulator

Sleep

Regulator

Hibernate

Regulator

I/O Supply

Vddio2

Vddio0

Vddio3

Vddio1

0.1 µF

Vddd

1 µF

Vdda

0.1 µF

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