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ADS5294IPFPR データシート(PDF) 11 Page - Texas Instruments

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部品番号 ADS5294IPFPR
部品情報  Octal Channel 14-Bit, 80 MSPS High-SNR and Low-Power ADC
PDF  67 Pages
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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ADS5294IPFPR データシート(HTML) 11 Page - Texas Instruments

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ADS5294
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SLAS776B – NOVEMBER 2011 – REVISED JULY 2012
Table 1. LVDS Timing at Different Sampling Frequencies - 2 Wire Interface, 7x Serialization (1)
LVDS Output Rate (MSPS)
Setup Time (tsu), ns
Hold Time (tH), ns
tPROG = (6/7) × T + tdelay, ns
(2)
Zero-Crossing of LCLKP to
Data Valid to Zero-
tPROG = delay from Input clock zero-cross
Data Becoming Invalid
Crossing of LCLKP
rising edge to frame clock zero cross (rising
Fs = 1/T
(both edges)
edge)
(both edges)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
80
0.34
0.57
0.55
0.8
8
9.5
11
65
0.35
0.64
0.8
1.1
8
9.5
11
50
0.7
0.9
1.2
1.5
8
9.5
11
40
1
1.3
1.6
1.85
8
9.5
11
30
1.7
2
2
2.3
8
9.5
11
20
2.9
3.2
3.2
3.5
8
9.5
11
10
6.5
6.7
6.7
7
8
9.5
11
(1)
Bit clock and Frame clock jitter has been included in the Setup and hold timing.
(2)
Values below correspond to tdelay, NOT tPROG
Table 2. LVDS Timing at Different Sampling Frequencies - 1 Wire Interface, 14x Serialization (1)
LVDS Output Rate (MSPS)
Setup Time (tsu), ns
Hold Time (tH), ns
tPROG = (5/7) × T + tdelay, ns
(2)
Zero-Crossing of LCLKP to
Data Valid to Zero-
tPROG = delay from Input clock zero-cross
Data Becoming Invalid
Crossing of LCLKP
rising edge to frame clock zero cross (rising
Fs = 1/T
(both edges)
edge)
(both edges)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
50
0.28
0.48
0.28
0.6
7.5
9
10.5
40
0.5
0.68
0.54
0.8
7.5
9
10.5
30
0.62
0.8
1
1.25
7.5
9
10.5
20
1.2
1.4
1.6
1.9
7.5
9
10.5
10
3.1
3.3
3.3
3.5
7.5
9
10.5
(1)
Bit clock and Frame clock jitter has been included in the Setup and hold timing.
(2)
Values below correspond to tdelay, NOT tPROG
Copyright © 2011–2012, Texas Instruments Incorporated
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