STA369BWS datasheet(80/89 Pages) STMICROELECTRONICS

80 / 89 page

STA369BWS

80/89

Doc ID 16861 Rev 4

6.22

Bad PWM detection registers (addr 0x4D, 0x4E, 0x4F)

STA369BWS implements a detection on PWM outputs which is able to verify if the output

signal has no zero crossing in a configurable time window. This check is useful to detect the

DC level in the PWM outputs. The checks are performed at logic level PWM so it is

implemented inside the PWM modulator logic.

In the case of ternary modulation, the detection threshold is computed as:

TH = ((BPTH * 2 + 1) / 128) * 100%

If the measured PWM duty cycle is detected greater or equal to TH for more than BPTIM

PWM periods, the corresponding PWM bit is set in register 0x4E.

In the case of binary modulation, there are two thresholds:

TH1 = ((64 + BPTH) / 128) * 100%

TH2 = ((64 - BPTH) / 128) * 100%

In this case, if the measured PWM duty cycle is outside the TH1 to TH2 range for more than

BPTIM PWM periods, the corresponding bit is set in register 0x4E.

6.23

Coefficient RAM CRC protection (addr 0x60-0x6C)

6.23.1

BQCHKE registers (addr 0x60 - 0x62)

BPTH[5]

BPTH[4]

BPTH[3]

BPTH[2]

BPTH[1]

BPTH[0]

Reserved

GDRC

001

BP4B

BP4A

BP3B

BP3A

BP2B

BP2A

BP1B

BP1A

000

BPTIM[7]

BPTIM[6]

BPTIM[5]

BPTIM[4]

BPTIM[3]

BPTIM[2]

BPTIM[1]

BPTIM[0]

000

BQCHKE[7]

BQCHKE[6]

BQCHKE[5]

BQCHKE[4]

BQCHKE[3]

BQCHKE[2]

BQCHKE[1]

BQCHKE[0]

000

BQCHKE[15]

BQCHKE[14]

BQCHKE[13]

BQCHKE[12]

BQCHKE[11]

BQCHKE[10]

BQCHKE[9]

BQCHKE[8]

000

BQCHKE[23]

BQCHKE[22]

BQCHKE[21]

BQCHKE[20]

BQCHKE[19]

BQCHKE[18]

BQCHKE[17]

BQCHKE[16]

000

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