TDA7590_09 datasheet(10/42 Pages) STMICROELECTRONICS

10 / 42 page

Pin description

TDA7590

10/42

HAD[6]

I/O

Host 8-bit data line 6. Host data bus and/or address lines when in multiplexed

mode.

HAD[5]

I/O

Host 8-bit data line 5. Host data bus and/or address lines when in multiplexed

mode.

HAD[4]

I/O

Host 8-bit data line 4. Host data bus and/or address lines when in multiplexed

mode.

COREVDD

Core power supply.

COREVSS

Core ground.

HAD[3]

I/O

Host 8-bit data line 3. Host data bus and/or address lines when in multiplexed

mode.

HAD[2]

I/O

Host 8-bit data line 2. Host data bus and/or address lines when in multiplexed

mode.

HAD[1]

I/O

Host 8-bit data line 1. Host data bus and/or address lines when in multiplexed

mode.

HAD[0]

I/O

Host 8-bit data line 0. Host data bus and/or address lines when in multiplexed

mode.

AA[3]

Address attributes line 3.Port A address attributes/chip select pins with

programmable polarity.

AA[2]

Address attributes line 2.Port A address attributes/chip select pins with

programmable polarity.

BR_N

Bus request. Asserted when port A requires bus mastership to perform off-

chip accesses.

BB_N

I/O

Bus busy. Asserted by port A when bus_busy_in_n is negated and BG_N is

asserted.

IOVDD

IO power supply.

IOVSS

IO ground.

WEN_N

Write enable.

OEN_N

Output enable.

AA[1]

Address attributes line 1.Port A address attributes/chip select pins with

programmable polarity.

AA[0]

Address attributes line 0.Port A address attributes/chip select pins with

programmable polarity.

BG_N

Bus grant. When asserted, Port A becomes the bus master elect. Bus

mastership

is attained when bus busy is negated by the current bus master.

AB[0]

Address bus line 0. Port A external address bus.

AB[1]

Address bus line 1. Port A external address bus.

IOVDD

IO power supply.

IOVSS

IO ground.

AB[2]

Address bus line 2. Port A external address bus.

Table 2.

Pin function (continued)

N°

Name

Type

Description

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