Single LNB Supply and Control Voltage Regulator

A8290

10

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

The Read/Write bit is used to determine the data transfer direc-

tion. If the Read/Write bit is high, the master reads the contents of

register 1, followed by register 2 if a further read is performed. If

the Read/Write bit is low, the master writes data to one of the two

Control registers. Note that multiple writes are not permitted. All

write operations must be preceded with the address.

The Acknowledge bit has two functions. It is used by the mas-

ter to determine if the slave device is responding to its address

and data, and it is used by the slave when the master is reading

data back from the slave. When the A8290 decodes the 7-bit ad-

dress field as a valid address, it responds by pulling SDA low

during the ninth clock cycle.

During a data write from the master, the A8290 also pulls SDA

low during the clock cycle that follows the data byte, in order to

indicate that the data has been successfully received. In both cas-

es, the master device must release the SDA line before the ninth

clock cycle, in order to allow this handshaking to occur.

During a data read, the A8290 acknowledges the address in the

same way as in the data write sequence, and then retains control

of the SDA line and send the data from register 1 to the master.

On completion of the eight data bits, the A8290 releases the SDA

line before the ninth clock cycle, in order to allow the master to

acknowledge the data. If the master holds the SDA line low dur-

ing this Acknowledge bit, the A8290 responds by sending the

data from register 2 to the master. Data bytes continue to be sent

to the master until the master releases the SDA line during the

Acknowledge bit. When this is detected, the A8290 stops sending

data and waits for a stop signal.

Interrupt Request

The A8290 also provides an interrupt request pin, IRQ, which

is an open-drain, active-low output. This output may be connect-

ed to a common IRQ line with a suitable external pull-up and can

from the master controller.

1

2

3

4

5

6

7

8

9

0

0

0

1

0

A1

A0

0

AK

AK

I0

D5

D4

D3

D2

D1

D0

I1

Control Data

Address

Start

W

Stop

SDA

SCL

0

0

0

1

0

A1

A0

1

AK

D6

D5

D4

D3

D2

D1

D0

D7

NAK

Status Register 1

Address

Start

R

Stop

1

2

3

4

5

6

7

8

9

SDA

SCL

0

0

0

1

0

A1

A0

1

AK

D6

D5

D4

D3

D2

D1

D0

D7

-

-

-

D3

D2

D1

D0

-

AK

NAK

Status Data in Register 2

Address

Start

R

Stop

Status Data in Register 1

1

2

3

4

5

6

7

8

9

SDA

SCL

acknowledge

from LNBR

acknowledge

from LNBR

acknowledge

from LNBR

no acknowledge

from master

no acknowledge

from master

acknowledge

from LNBR

acknowledge

from LNBR

Write to Register

Read One Byte from Register

Read Multiple Bytes from Register