LTC6930 datasheet(15/28 Pages) LINER

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LTC6995-1/LTC6995-2

699512f

For more information www.linear.com/6995

applicaTions inForMaTion

Power-On Reset (POR) Function

When power is applied to the LTC6995 the output is held

low for tSTART, then takes on the value of the POL bit as the

clock cycle begins. If POL = 0 (DIVCODE < 8) the output

will remain low for a programmable interval of tSTART +

1/2 tOUT, assuming the RST pin is inactive. This makes the

LTC6995 useful as a programmable long-time power-on

reset (POR), with the low output used to hold a system

in reset for a fixed period after power is applied. Timing

begins when the V+ supply exceeds approximately 1.4V.

TopreventadditionaloutputtransitionsaftertheinitialPOR

time, the oscillator can be disabled by removing the SET

pin current. This prevents the internal master oscillator

output from clocking the frequency dividers or output,

while keeping it biased so it can resume operation quickly.

The easiest way to implement this feature is to connect

RSET between the SET and OUT pins.

Figure 12 shows the basic power-on reset function. When

the half cycle times out, the output goes high, eliminates

the SET pin current, and stops additional OUT pin transi-

tions. The output remains high until the device is reset by

driving the RST input or power is cycled off then back on.

The POR interval is only one half of an oscillator period so

component selection is slightly different. Table 2 provides

the component values required for one half cycle time

intervals. Timing starts after a short startup delay time

following the application of the V+ supply.

LTC6995-1

tPOR = 1 SECOND FOR VALUES SHOWN

POL = 0

DIVCODE = 3

NDIV = 512

RST = V+ FOR LTC6995-2

RST

GND

SET

OUT

V+

DIV

RSET

191k

280k

0.1µF

2.25V TO 5.5V

POR

OUT

POL = 0

699512 F12

tDELAY

(1/2 tOUT)

tSTART

TIMER STOPPED

~1.4V STARTS TIMER

POWER-ON RESET

V+

Figure 12. Active Low Power-On Reset

(1 Second Interval Example)

Table 2. Power-On Reset (POR). One Shot, One Half Cycle Delay Programming

Output Low During Time Interval, POL = 0

DIVCODE

tDELAY TIME INTERVAL (1/2 tOUT)

R1 (kΩ)

R2 (kΩ)

~RSET (kΩ)

512µs to 8.2ms

Open

Short

tDELAY(MS) • 97.6

4.1ms to 65.5ms

976

102

tDELAY(MS) • 12.2

32.8ms to 524.3ms

976

182

tDELAY(MS) • 1.5

262.1ms to 4.2sec

1000

280

tDELAY(SEC) • 190.7

2.1sec to 33.6sec

1000

392

tDELAY(SEC) • 23.8

16.8sec to 4.5min

1000

523

tDELAY(MIN) • 178.6

2.2min to 35.8min

1000

681

tDELAY(MIN) • 22.7

17.9min to 4.8hrs

1000

887

tDELAY(HR) • 167.6

Note: Power-On Reset Time = tDELAY + tSTART

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