| データシートサーチシステム |
|
LTC6930 データシート(PDF) 20 Page - Linear Technology |
|
|
|||||||||||||||||||||||||||||
LTC6930 データシート(HTML) 20 Page - Linear Technology |
|
20 / 28 page ![]() LTC6995-1/LTC6995-2 20 699512f For more information www.linear.com/6995 Digital Frequency Control The control voltage can be generated by a DAC (digital- to-analog converter), resulting in a digitally-controlled frequency. Many DACs allow for the use of an external reference. If such a DAC is used to provide the VCTRL voltage, the VSET dependency can be eliminated by buffer- ing VSET and using it as the DAC’s reference voltage, as shown in Figure 21. The DAC’s output voltage now tracks any VSET variation and eliminates it as an error source. The SET pin cannot be tied directly to the reference input of the DAC because the current drawn by the DAC’s REF input would affect the frequency. ISET Extremes (Master Oscillator Frequency Extremes) When operating with ISET outside of the recommended 1.25µA to 20µA range, the master oscillator operates outside of the 62.5kHz to 1MHz range in which it is most accurate. The oscillator can still function with reduced accuracy for ISET<1.25µA.Atapproximately500nA,theoscillatoroutput will be frozen in its current state. The output could halt in a high or low state. This avoids introducing short pulses when frequency modulating a very low frequency output. At the other extreme, it is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. applicaTions inForMaTion LTC6995-1 2.25V TO 5.5V 0.1µF OUT R1 1M R2 523k RSET 178k RST GND SET OUT V+ DIV CPW 470pF RPW 2.26k 699512 F19a 60 SECONDS 1µs PULSE WIDTH VRST(RISING) V+ tPULSE = –RPW • CPW • In tPULSE ≈ –2.26kΩ • 470pF • In(1 – 0.61) tPULSE ≈ 1µs 1– ( ) LTC6995-2 2.25V TO 5.5V 0.1µF 699512 F19b OUT R1 523k R2 1M 60 SECONDS 0.9µs PULSE WIDTH VRST(FALLING) V+ tPULSE = –RPW • CPW • In tPULSE ≈ –2.26kΩ • 470pF • In(0.43) tPULSE ≈ 0.9µs RSET 178k RST GND SET OUT V+ DIV CPW 470pF RPW 2.26k ( ) 699512 F20 LTC6995-1 RST GND SET OUT V+ DIV R1 C1 0.1µF R2 RSET RVCO VCTRL V+ Figure 19a. Self-Resetting Circuit (DIVCODE = 4) Figure 19b. Self-Resetting Circuit (DIVCODE = 11) Figure 20. Voltage-Controlled Oscillator |
|
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |