LTC6930 datasheet(21/28 Pages) LINER

21 / 28 page

LTC6995-1/LTC6995-2

699512f

For more information www.linear.com/6995

Frequency Modulation and Settling Time

The LTC6995 will respond to changes in ISET up to a –3dB

bandwidth of 0.4 • fOUT.

Following a 2

× or 0.5× step change in ISET, the output

frequency takes less than one cycle to settle to within 1%

of the final value.

Power Supply Current

The power supply current varies with frequency, supply

voltage and output loading. It can be estimated under

any condition using the following equation. This equation

ignores CLOAD (valid for CLOAD < 1nF) and assumes the

output has 50% duty cycle.

IS(TYP) ≈ V+ • fMASTER • 7.8pF +

V+

420k

Ω

V+

2 •RLOAD

+ 1.8 •ISET +50µA

Supply Bypassing and PCB Layout Guidelines

The LTC6995 is a 2.2% accurate silicon oscillator when

used in the appropriate manner. The part is simple to use

applicaTions inForMaTion

–

699512 F21

LTC6995

RST

GND

SET

OUT

V+

DIV

0.1µF

RSET

V+

RVCO

V+

0.1µF

1/2

LTC6078

LTC1659

V+

VCC

REF

GND

VOUT

µP

DIN

CLK

CS/LD

1MHz • 50kΩ

1024 • NDIV • RVCO

fOUT =

DIN = 0 TO 4095

• 1 +

–

RVCO

RSET

DIN

4096

(

)

0.1µF

Figure 21. Digitally-Controlled Oscillator

and by following a few rules, the expected performance is

easily achieved. Adequate supply bypassing and proper

PCB layout are important to ensure this.

Figure22showsexamplePCBlayoutsforboththeTSOT-23

and DFN packages using 0603 sized passive components.

The layouts assume a two layer board with a ground plane

layer beneath and around the LTC6995. These layouts are

a guide and need not be followed exactly.

1. Connect the bypass capacitor, C1, directly to the V+ and

GND pins using a low inductance path. The connection

from C1 to the V+ pin is easily done directly on the top

layer. For the DFN package, C1’s connection to GND is

alsosimplydoneonthetoplayer.FortheTSOT-23,OUT

can be routed through the C1 pads to allow a good C1

GND connection. If the PCB design rules do not allow

that,C1’sGNDconnectioncanbeaccomplishedthrough

multiple vias to the ground plane. Multiple vias for both

the GND pin connection to the ground plane and the

C1 connection to the ground plane are recommended

to minimize the inductance. Capacitor C1 should be a

0.1µF ceramic capacitor.

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