STM32F407IGH6 datasheet(102/185 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F405xx, STM32F407xx

102/185

DocID022152 Rev 4

5.3.11

PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

interferences (see Table 43: EMI characteristics). It is available only on the main PLL.

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

fPLL_IN and fMod must be expressed in Hz.

As an example:

If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by

equation 1:

Jitter(3)

Master I2S clock jitter

Cycle to cycle at

12.288 MHz on

48KHz period,

N=432, R=5

RMS

peak

±280

Average frequency of

12.288 MHz

N = 432, R = 5

on 1000 samples

-90

WS I2S clock jitter

Cycle to cycle at 48 KHz

on 1000 samples

-400

IDD(PLLI2S)(4)

PLLI2S power consumption on

VDD

VCO freq = 192 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLI2S)(4)

PLLI2S power consumption on

VDDA

VCO freq = 192 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design, not tested in production.

3. Value given with main PLL running.

4. Based on characterization, not tested in production.

Table 36. PLLI2S (audio PLL) characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 37. SSCG parameters constraint

Symbol

Parameter

Min

Typ

Max(1)

Unit

fMod

Modulation frequency

KHz

Peak modulation depth

0.25

MODEPER * INCSTEP

215

−1-

1. Guaranteed by design, not tested in production.

MODEPER

round fPLL_IN 4fMod

()

⁄

[]

MODEPER

round 10

410

()

⁄

[]

250

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