OMAP3530ECBC72 datasheet(172/264 Pages) TI1

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OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

www.ti.com

Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNFI3

Maximum device select generation delay from

6.5

9.1

13.7

internal functional clock

GNFI4

Maximum address latch enable generation delay

6.5

9.1

13.7

from internal functional clock

GNFI5

Maximum command latch enable generation

6.5

9.1

13.7

delay from internal functional clock

GNFI6

Maximum output enable generation delay from

6.5

9.1

13.7

internal functional clock

GNFI7

Maximum write enable generation delay from

6.5

9.1

13.7

internal functional clock

GNFI8

Maximum functional clock skew

100

170

200

Table 6-11. GPMC/NAND Flash Interface Timing Requirements

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNF12(1) tacc(DAT)

Data maximum access time

J(2)

GPMC_FCLK

cycles

(1)

The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the

active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.

(2)

J = AccessTime * (TimeParaGranularity + 1)

Table 6-12. GPMC/NAND Flash Interface Switching Characteristics

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tR(DO)

Rise time, output

2.0

data

tF(DO)

Fall time, output

2.0

data

GNF0

tw(nWEV)

Pulse duration,

A(1)

gpmc_nwe valid

time

GNF1

td(nCSV-nWEV)

Delay time,

B(2) – 0.2

B(2) + 2.0

B(2) – 0.2

B(2) + 2.6

B(2) – 0.2

B(2) + 3.7

gpmc_ncsx(13)

valid to

gpmc_nwe valid

GNF2

tw(CLEH-nWEV)

Delay time,

C(3) – 0.2

C(3) + 2.0

C(3) – 0.2

C(3) + 2.6

C(3) – 0.2

C(3) + 3.7

gpmc_nbe0_cle

high to gpmc_nwe

valid

GNF3

tw(nWEV-DV)

Delay time,

D(4) – 0.2

D(4) + 2.0

D(4) – 0.2

D(4) + 2.6

D(4) – 0.2

D(4) + 3.7

gpmc_d[15:0]

valid to

gpmc_nwe valid

GNF4

tw(nWEIV-DIV)

Delay time,

E(5) – 0.2

E(5) + 2.0

E(5) – 0.2

E(5) + 2.6

E(5) – 0.2

E(5) + 3.7

gpmc_nwe invalid

to gpmc_d[15:0]

invalid

GNF5

tw(nWEIV-CLEIV)

Delay time,

F(6) – 0.2

F(6) + 2.0

F(6) – 0.2

F(6) + 2.6

F(6) – 0.2

F(6) + 3.7

gpmc_nwe invalid

gpmc_nbe0_cle

invalid

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

172

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