OMAP3530ECBC72 datasheet(175/264 Pages) TI1

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GPMC_FCLK

gpmc_ncsx

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

gpmc_a[16:1]_d[15:0]

gpmc_waitx

DATA

GNF10

GNF13

GNF14

GNF15

GNF12

030-034

GPMC_FCLK

gpmc_ncsx

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

gpmc_nwe

gpmc_a[16:1]_d[15:0]

DATA

GNF0

GNF1

GNF4

GNF6

GNF9

GNF3

030-035

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

Figure 6-15. GPMC/NAND Flash – Data Read Cycle Timing(1)(2)(3)

(1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock

edge. The GNF12 value must be stored inside AccessTime register bit field.

(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1.

Figure 6-16. GPMC/NAND Flash – Data Write Cycle Timing

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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

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OMAP3530ECBC72 データシート(PDF) 175 Page - Texas Instruments

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