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OMAP3530ECBC72 データシート(PDF) 201 Page - Texas Instruments |
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OMAP3530ECBC72 データシート(HTML) 201 Page - Texas Instruments |
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201 / 264 page  6.6 Serial Communications Interfaces 6.6.1 Multichannel Buffered Serial Port (McBSP) Timing 6.6.1.1 McBSP in Normal Mode OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct serial interface between the OMAP3530/25 device and other devices in a system such as other application devices or codecs. It can accommodate a wide range of peripherals and clocked frame-oriented protocols (I2S, PCM, and TDM) due to its high level of versatility. The McBSP1-5 modules may support two types of data transfer at the system level: • The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge and captured on the same edge (one clock period later). • The half-cycle mode, for which one half clock period is used to transfer the data, generated on one edge and captured on the opposite edge (one half clock period later). Note that a new data is generated only every clock period, which secures the required hold time. The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be configured accordingly with the external peripheral (activation edge capability) and the type of data transfer required at the system level. The OMAP3530/25 McBSP1-5 timing characteristics are described for both rising and falling activation edges. McBSP1 supports: • 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins. • 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are internally looped back via software configuration, respectively, to the clkr and fsr internal signals for data receive. McBSP2, 3, 4, and 5 support only the 4-pin mode. The following sections describe the timing characteristics for applications in normal mode (that is, OMAP3530/25 McBSPx connected to one peripheral) and TDM applications in multipoint mode. Table 6-42. McBSP Timing Conditions—Normal Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2 ns tF Input signal fall time 2 ns Output Conditions CLOAD Output load capacitance 10 pF Table 6-43. McBSP Output Clock Pulse Duration NO. PARAMETER OPP3 OPP2 UNIT MIN MAX MIN MAX Inputs and Outputs McBSP1 tc(CLK) Cycle time, mcbsp1_clkx / mcbsp1_clkr (multiplexing mode 20.83 41.67 ns 0) McBSP2 tc(CLK) Cycle time, mcbsp2_clkx (multiplexing mode 0) 20.83 41.67 ns McBSP3 tc(CLK) Cycle time, IO set 1 (multiplexing mode 0) 31.25 62.50 ns mcbsp3_clkx IO set 2 (multiplexing mode 1) 20.83 41.67 IO set 3 (multiplexing mode 2) 20.83 41.67 McBSP4 tc(CLK) Cycle time, IO set 1 (multiplexing mode 0) 20.83 41.67 ns mcbsp4_clkx IO set 2 (multiplexing mode 2) 31.25 62.50 McBSP5 tc(CLK) Cycle time, mcbsp5_clkx (multiplexing mode 1) 31.25 62.50 ns Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 201 |
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