AD7655AST datasheet(18/28 Pages) AD

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AD7655

Rev. B | Page 18 of 28

CONVERSION CONTROL

Figure 21 shows a detailed timing diagram of the conversion

process. The AD7655 is controlled by the signal CNVST,

which initiates conversion. Once initiated, it cannot be

restarted or aborted, even by the power-down input, PD,

until the conversion is complete. The CNVST signal operates

independently of the CS and RD signals.

BUSY

ACQUIRE

CONVERT A

ACQUIRE

CONVERT

CONVERT B

t12

t14

t15

t13

t11

t10

EOC

CNVST

MODE

Figure 21. Basic Conversion Timing

Although CNVST is a digital signal, it should be designed with

special care with fast, clean edges and levels, and with minimum

overshoot and undershoot or ringing.

For applications where the SNR is critical, the CNVST signal

should have very low jitter. One solution is to use a dedicated

oscillator for CNVST generation or, at least, to clock it with a

high frequency low jitter clock, as shown in Figure 17.

In impulse mode, conversions can be automatically initiated. If

CNVST is held low when BUSY is low, the AD7655 controls the

acquisition phase and automatically initiates a new conversion.

By keeping CNVST low, the AD7655 keeps the conversion

process running by itself. Note that the analog input has to be

settled when BUSY goes low. Also, at power-up, CNVST should

be brought low once to initiate the conversion process. In this

mode, the AD7655 can sometimes run slightly faster than the

guaranteed limits of 888 kSPS in impulse mode. This feature

does not exist in normal mode.

DIGITAL INTERFACE

The AD7655 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7655 digital interface accommodates either 3 V or 5 V logic

when the OVDD supply pin of the AD7655 is connected to the

host system interface digital supply.

The two signals, CS and RD, control the interface. When at

least one of these signals is high, the interface outputs are in

high impedance. Usually CS allows the selection of each

AD7655 in multicircuit applications and is held low in a single

AD7655 design. RD is generally used to enable the conversion

result on the data bus. In parallel mode, signal A/B allows the

choice of reading either the output of Channel A or Channel B,

whereas in serial mode, signal A/B controls which channel is

output first.

Figure 22 details the timing when using the RESET input. Note

the current conversion, if any, is aborted and the data bus is

high impedance while RESET is high.

RESET

DATA

BUS

BUSY

CNVST

Figure 22. Reset Timing

PARALLEL INTERFACE

The AD7655 is configured to use the parallel interface when

SER/PAR is held low.

Master Parallel Interface

Data can be read continuously by tying CS and RD low, thus

requiring minimal microprocessor connections. However, in

this mode the data bus is always driven and cannot be used in

shared bus applications (unless the device is held in RESET).

Figure 23 details the timing for this mode.

t17

BUSY

DATA

BUS

t16

NEW A

OR B

PREVIOUS CHANNEL A

OR B

PREVIOUS CHANNEL B

OR NEW A

t10

CS = RD = 0

EOC

CNVST

Figure 23. Master Parallel Data Timing for Reading (Continuous Read)

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