AD7887ARM datasheet(18/24 Pages) AD

18 / 24 page

AD7887

Rev. D | Page 18 of 24

MICROPROCESSOR INTERFACING

The serial interface on the AD7887 allows the part to be directly

connected to a range of many different microprocessors. This

section explains how to interface the AD7887 with some of the

more common microcontroller and DSP serial interface

protocols.

AD7887 to TMS320C5x

The serial interface on the TMS320C5x uses a continuous serial

clock and frame synchronization signals to synchronize the data

transfer operations with peripheral devices like the AD7887.

The CS input allows easy interfacing with an inverter between

the serial clock of the TMS320C5x and the AD7887 being the

only glue logic required. The serial port of the TMS320C5x is

set up to operate in burst mode with internal CLKX (Tx serial

clock) and FSX (Tx frame sync). The serial port control register

(SPC) must have the following setup: FO = 0, FSM = 1,

MCM = 1, and TXM = 1. The connection diagram is shown in

Figure 22

AD78871

DOUT

DIN

SCLK

TMS320C5x1

1ADDITIONAL PINS OMITTED FOR CLARITY.

CLKX

CLKR

FSX

FSR

Figure 22. Interfacing to the TMS320C5x

AD7887 to ADSP-21xx

The ADSP-21xx family of DSPs are easily interfaced to the

AD7887 with an inverter between the serial clock of the ADSP-

21xx and the AD7887. This is the only glue logic required. The

SPORT control register should be set up as follows:

Table 7. SPORT0 Control Register Setup

Setting

Description

TFSW = RFSW = 1

Alternative framing

INVRFS = INVTFS = 1

Active low frame signal

DTYPE = 00

Right justify data

SLEN = 1111

16-bit data-word

ISCLK = 1

Internal serial clock

TFSR = RFSR = 1

Frame every word

IRFS = 0

ITFS = 1

The connection diagram is shown in Figure 23. The ADSP-21xx

has the TFS and RFS of the SPORT tied together, with TFS set

as an output and RFS set as an input. The DSP operates in

alternate framing mode, and the SPORT control register is set

up as described in Table 7. The frame synchronization signal

generated on the TFS is tied to CS and, as with all signal

processing applications, equidistant sampling is necessary. In

this example however, the timer interrupt is used to control the

sampling rate of the ADC and, under certain conditions,

equidistant sampling cannot be achieved.

The timer registers are loaded with a value that will provide an

interrupt at the required sample interval. When an interrupt is

received, a value is transmitted with TFS/DT (ADC control

word). The TFS is used to control the RFS and hence the

reading of data. The frequency of the serial clock is set in the

SCLKDIV register. When the instruction to transmit with TFS

is given (that is, AX0 = TX0), the state of the SCLK is checked.

The DSP waits until the SCLK has gone high, low, and high

again before a transmission starts. If the timer and SCLK values

are chosen such that the instruction to transmit occurs on or

near the rising edge of SCLK, the data may be transmitted or it

may wait until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3, a

SCLK of 2 MHz is obtained and eight master clock periods will

elapse for every one SCLK period. If the timer registers are

loaded with the value 803, 100.5 SCLKs will occur between

interrupts and subsequently between transmit instructions. This

situation results in nonequidistant sampling because the

transmit instruction is occurring on an SCLK edge. If the

number of SCLKs between interrupts is a whole integer number

of N, equidistant sampling will be implemented by the DSP.

AD78871

DOUT

DIN

SCLK

1ADDITIONAL PINS OMITTED FOR CLARITY.

SCLK

RFS

TFS

ADSP-21xx1

Figure 23. Interfacing to the ADSP-21xx

AD7887 to DSP56xxx

The connection diagram in Figure 24 shows how the AD7887

can be connected to the SSI (synchronous serial interface) of

the DSP56xxx family of DSPs from Motorola. The SSI is

operated in synchronous mode (SYN bit in CRB = 1) with an

internally generated 1-bit clock period frame sync for both Tx

and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word

length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. An

inverter is also necessary between the SCLK from the DSP56xxx

and the SCLK pin of the AD7887, as shown in Figure 24.

DOUT

DIN

SCLK

1ADDITIONAL PINS OMITTED FOR CLARITY.

DSP56xxx1

AD78871

SCK

SRD

STD

SC2

Figure 24. Interfacing to the DSP56xxx

AD7887ARM データシート(PDF) 18 Page - Analog Devices

AD7887ARM データシート(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

データシートダウンロード

リンク URL

AD7887ARM データシート(PDF) 18 Page - Analog Devices

AD7887ARM データシート(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

データシート ダウンロード

リンク URL

データシートダウンロード