C2.5X6.3MM-RAD datasheet(12/38 Pages) SILABS

部品番号	C2.5X6.3MM-RAD

部品情報	Low-power sleep mode On-hook transmission Loop or ground start operation Smooth polarity reversal

PDF	38 Pages

Scroll/Zoom	100%

メーカー	SILABS [Silicon Laboratories]

ホームページ	http://www.silabs.com

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12 / 38 page

Si3226/7

Si3208/9

Preliminary Rev. 0.33

Table 11. Switching Characteristics—PCM Highway Interface

(VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL =20pF)

Parameter

Symbol

Test

Conditions

Min1

Typ1

Max1

Units

PCLK Period

122

—

3906

Valid PCLK Inputs

—

512

768

1.024

1.536

1.544

2.048

4.096

8.192

—

kHz

MHz

FSYNC Period2

tfs

—125

—

µs

PCLK Duty Cycle Tolerance

tdty

FSYNC Jitter Tolerance

tjitter

—

±120

Rise Time, PCLK

—

Fall Time, PCLK

—

Delay Time, PCLK Rise to DTX Active

td1

—

Delay Time, PCLK Rise to DTX

Transition

td2

—

Delay Time, PCLK Rise to DTX

Tristate3

td3

—

Setup Time, FSYNC to PCLK Fall

tsu1

—

Hold Time, FSYNC to PCLK Fall

th1

—

Setup Time, DRX to PCLK Fall

tsu2

—

Hold Time, DRX to PCLK Fall

th2

—

FSYNC Pulse Width

twfs

—125 µs–tp

Notes:

1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4 V, VIL =0.4 V.

2. FSYNC source is assumed to be 8 kHz under all operating conditions.

3. Spec applies to PCLK fall to DTX tristate when that mode is selected.

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